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3-D Multi-Chip stacking is a promising technology to overcome the “memory wall”, “power wall”, “ILP wall”, and “utilization wall”. However, a chip to be stacked should be low-power enough to avoid heat issue. On the other hand, such system can benefit from its scalability, flexibility, short time-to-market, especially wide and short latency chip interconnect drives changes on microprocessor architecture. In this presentation, we introduce a scalable heterogeneous Multi-Core/Multi-Chip architecture that drastically reduced the operating clock frequency. Two chips will be shown that run at 50MHz for Digital TV applications, while the performance is comparable to 3GHz Core2Duo processor.