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A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

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3 Author(s)
Shimazaki, Y. ; Renesas Electron. Corp., Tokyo, Japan ; Miura, N. ; Kuroda, T.

We propose 3-D integrated mobile phone system utilizing an inductive-coupling link. To realize energy efficient 3-die stacking, a slew-rate controlled footer switch scheme and a superposition of magnetic field scheme are proposed. By using a place-and-route model of a coil, we demonstrate that a commercial layout tool can handle the inductive-coupling link module successfully. Performance of the proposed circuit is estimated as 5.184Gbps/ch and 6.1pJ/b for 2-die stacking and 9.5pJ/b for 3-die stacking. The area efficiency is 592μm2/Gbps, which is 1/330 of the prior art.

Published in:

Cool Chips XV (COOL Chips), 2012 IEEE

Date of Conference:

18-20 April 2012