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This paper presents an improved algorithm for power hardware-in-loop (PHIL) simulation that takes the errors introduced by the interface equipment into account. Through modeling and analysis of a PHIL simulation circuit, which is composed of a voltage-source converter and a simple network, the impact of the bandwidth of the interface amplifier and equipment on the PHIL simulation is examined. Based on the analysis, an improved algorithm is proposed that uses additional interface filters (implemented in hardware and/or software) rather than the use of previously attempted compensation techniques. More stable and accurate results can be obtained by using the new algorithm. The validity of the proposed algorithm is verified through a software case study and hardware case studies.