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10 bit, 25 MBz, 15 mW CMOS pipelined subranging ADC

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2 Author(s)
Shang-Ching Dong ; Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA ; Carlson, B.S.

A new scheme to implement the pipelined subranging ADC is presented in this paper. Source follower structured subtractors and latch structured comparators enable the ADC to operate at 25 MHz sampling rate with very low power dissipation. Higher sampling rate is achievable with the trade-off of power consumption. The maximum resolution is 10 bits. The circuits can also be used in 3-V powered systems. The die area is less than 0.36 mm2 in 0.8 μm process

Published in:

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on  (Volume:3 )

Date of Conference:

9-12 Jun 1997