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In this paper, a methodology for the power-optimal design of high-resolution low-bandwidth switched-capacitor ΔΣ modulators (ΔΣMs) is presented. The most power-efficient ΔΣ architecture is identified among single-loop feedback and feedforward topologies with different loop orders N, oversampling ratios OSR, and quantizer resolutions B. Based on this study, an experimental prototype has been implemented in a 0.18- μm CMOS process. It achieves a signal-to-noise ratio of 95 dB over a signal bandwidth fBW of 10 kHz. The prototype operates with a 1.28-MHz sampling rate and consumes 210 μW from a 1.8-V supply.