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A Power-Optimal Design Methodology for High-Resolution Low-Bandwidth SC \Delta \Sigma Modulators

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5 Author(s)
Porrazzo, S. ; Electr. Eng. Dept., Eindhoven Univ. of Technol., Eindhoven, Netherlands ; Cannillo, F. ; Van Hoof, C. ; Cantatore, E.
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In this paper, a methodology for the power-optimal design of high-resolution low-bandwidth switched-capacitor ΔΣ modulators (ΔΣMs) is presented. The most power-efficient ΔΣ architecture is identified among single-loop feedback and feedforward topologies with different loop orders N, oversampling ratios OSR, and quantizer resolutions B. Based on this study, an experimental prototype has been implemented in a 0.18- μm CMOS process. It achieves a signal-to-noise ratio of 95 dB over a signal bandwidth fBW of 10 kHz. The prototype operates with a 1.28-MHz sampling rate and consumes 210 μW from a 1.8-V supply.

Published in:

Instrumentation and Measurement, IEEE Transactions on  (Volume:61 ,  Issue: 11 )

Date of Publication:

Nov. 2012

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