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A low power 100 MHz all digital delay-locked loop

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2 Author(s)
Bum-Sik Kim ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Lee-Sup Kim

All digital DLL is designed for synchronization of high frequency VLSI system with low power consumption and small area. Two new design method features are presented. First, the operation is described by Verilog HDL and verified. Second, using the circuit level simulations and optimizations, low power consumption and high speed is achieved. The simulation results show that the power consumption is 3.2 mW at 100 MHz, 2.0 V supply voltage without driver buffers; the area is 0.1 mm2 and the proposed DLL has no jitter

Published in:

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on  (Volume:3 )

Date of Conference:

9-12 Jun 1997

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