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Low-power globally asynchronous locally synchronous design using self-timed circuit technology

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2 Author(s)
Shyh-Jye Jou ; Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan ; I-Yao Chuang

In this paper an efficient implementation of self-timed circuits whose hardware and control signals are significantly reduced is first proposed. By applying Globally Asynchronous Locally Synchronous (GALS) design techniques, the hardware overhead is further reduced. GALS and synchronous version of 8-bit fully pipelined array multipliers are implemented for comparisons. The results show that GALS version has smaller peak current, less power consumption under variable workload with small hardware overhead as compared to synchronous version

Published in:

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on  (Volume:3 )

Date of Conference:

9-12 Jun 1997