Cart (Loading....) | Create Account
Close category search window
 

Global Multiple-Valued Clock Approach for High- Performance Multi-phase Clock Integrated Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Menon, R.P. ; Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA ; Thornton, M.A.

Some high performance digital integrated circuits use multi-phase clock distribution systems with level-sensitive latches as clocked storage elements. A set of N periodic non-overlapping binary clock signals propagate over each of the clock phase distribution networks and drive disjoint subsets of level-sensitive latches providing enhanced throughput and performance. This performance enhancement can result in increased area characteristics since the individual distribution networks are required for each clock phase. The method presented in this paper overcomes this problem by using a single global clock distribution network for a multi-valued (MV) clock signal in combination with level-sensitive latches designed to be transparent for a specific portion of the global MV clock signal. This approach is compatible with conventional binary logic since the only non-binary components required are the global clock generator and a modified literal selection gate that can be implemented as small analog circuits. A purely binary implementation approach is also described where the MV clock signal is replaced by a binary encoded signal and the phase-sensitive latches are implemented through the inclusion of a decoding function. This approach allows for implementation of the method using commercially available FPGA devices or a standard cell library containing only binary logic cells.

Published in:

Multiple-Valued Logic (ISMVL), 2012 42nd IEEE International Symposium on

Date of Conference:

14-16 May 2012

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.