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A new optimization cost model for VLSI standard cell placement

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5 Author(s)
P. Y. S. Cheung ; Dept. of Electr. & Electron. Eng., Hong Kong Univ., Hong Kong ; C. S. K. Yeung ; S. K. Tse ; C. K. Yuen
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In this paper, we propose a new optimization cost model for VLSI placement. It distinguishes itself from the traditional wire-length cost model by having direct impact on the quality of the detailed routing phase. We also extend the well-known simulated annealing standard cell placement algorithm by applying our new cost model. Experimental results show that we got 13% layout area reduction compared to traditional wire length model, 11% reduction to commercial tool

Published in:

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on  (Volume:3 )

Date of Conference:

9-12 Jun 1997