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This paper overviews a number of ΣΔ modulation techniques to implement efficient analog-to-digital converters intended for low-voltage wideband multimode wireless telecom systems. The ΣΔ architectures under study combine different strategies-unity signal transfer function (USTF), resonation, loop-filter order reconfiguration, and concurrency-in order to increase performance while keeping high robustness against circuit errors. Practical considerations involving timing issues-derived from the combined use of different noise-shaping techniques-are analyzed in order to evaluate the feasibility of the proposed ΣΔ topologies. As an application, the design, circuit implementation, and experimental characterization of a flexible 1.2-V 90-nm CMOS sixth-order three-stage cascade SC ΣΔ modulator is presented. The modulator uses local resonation in the last two stages and USTF and programmable (either three or five levels) quantization in all stages. The chip reconfigures its loop-filter order (second, fourth, sixth order) and the clock frequency (from 40 to 240 MHz) and scales the power consumption according to required specifications. These reconfiguration strategies are combined with the capability of concurrency in order to digitize up to three different wireless standards simultaneously. Experimental measurements show the flexibility of the proposed circuit, featuring a programmable noise shaping within a 100-kHz-10-MHz signal band, with adaptive power dissipation, thus demonstrating to be a suitable solution to digitize signals in future software-defined-radio mobile terminals.