Behavioral model of a 1.8 V 6b CMOS flash ADC based on device parameters

A hierarchical behavioral model of a submicron 6 bit CMOS flash analog to digital converter is presented. Circuit parameters are extracted from process dependent device data using an extension of the g/sub m//I/sub D/ methodology for use in the behavioral model. In using this approach, the model will track changes in physical device geometries without the need for re-characterization. The comparator model is validated against SPICE and system level simulation results are presented for the full converter.