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Behavioral model of a 1.8 V 6b CMOS flash ADC based on device parameters

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4 Author(s)
Pennell, M.J. ; Motorola SPS, Tempe, AZ, USA ; Hasan, M. ; Allee, D.R. ; Xie, W.

A hierarchical behavioral model of a submicron 6 bit CMOS flash analog to digital converter is presented. Circuit parameters are extracted from process dependent device data using an extension of the g m/ID methodology for use in the behavioral model. In using this approach, the model will track changes in physical device geometries without the need for re-characterization. The comparator model is validated against SPICE and system level simulation results are presented for the full converter

Published in:

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on  (Volume:3 )

Date of Conference:

9-12 Jun 1997