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A combined hardware selection, resource sharing and clock optimization for pipelined data-path synthesis

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3 Author(s)
Shin-ya Furasawa ; Dept. of Electron., Kyoto Univ., Japan ; V. G. Mashnyaga ; K. Tamaru

This paper presents a new approach for time constrained synthesis of pipelined data-paths. The method improves on previous work in the synthesis by being able to integrate clock optimization and resource sharing with functional pipelining and library mapping. Experiments on several benchmarks show that such formulation ensures efficient exploration of delay-area trade offs and results in circuit structure with a near optimal area under given throughput constraint

Published in:

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on  (Volume:3 )

Date of Conference:

9-12 Jun 1997