Power estimation considering statistical IC parametric variations

Statistical perturbations of process parameters may change propagation delays and alter the switching activity in the circuit due to glitches. In this paper, the problem of estimating glitch/hazard power in CMOS circuits is addressed. A probabilistic min/max delay model is used, where the variation of delays between the minimum and maximum delay may follow any given discrete probability distribution. The first part of this work considers glitching activity assuming fixed gate delays with instantaneous rise/fall times. Next, this is refined to incorporate the effects of fixed transition times. Experimental results on benchmark circuits show that a significant amount of power is dissipated in hazards and glitches and that the hazardous part of power dissipation is sensitive to variations in gate delays.