Cart (Loading....) | Create Account
Close category search window

Photoemission yield and the electron escape depth determination in metal–oxide–semiconductor structures on N+-type and P+-type silicon substrates

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Przewlocki, H.M. ; Institute of Electron Technology, Al. Lotnikow 32/46, PL 02-668 Warsaw, Poland ; Brzezinska, D. ; Engstrom, O.

Your organization might have access to this article on the publisher's site. To check, click on this link: 

This article gives a quantitative analysis of electron photoemission yield from N+-type and P+-type substrates of MOS structures. Based on this analysis, a method is presented to estimate both the scattering length, , of electrons in the image force potential well and of photoelectron escape depth, xesc, from the semiconductor substrate. This method was used to estimate the scattering length and the escape depth from the substrates of Al-SiO2-Si (N+-type and P+-type) structures. It was found that for N+-type substrate structures the scattering in the image force potential well has a dominating influence on the photoemission yield while for P+-type substrate structures both the scattering in the image force potential well and the photoemission from the subsurface regions of the photoemitter play important roles. It was found that the scattering length in the image force potential well was equal to  = 6.7–6.9 nm for structures on both N+ and P+ substrates, produced in the same processing conditions. For structures on P+ substrates, the escape depth was found to be equal to xesc = 8–9 nm. The scattering length, , determined in this study is considerably larger than the one reported previously ( = 3.4 nm) for similar MOS structures. The escape depth xesc determined in this study is also considerably larger than the escape depth determined previously (xesc = 1.2–2.5 nm) for the external photoemission from uncovered silicon surfaces into vacuum.

Published in:

Journal of Applied Physics  (Volume:111 ,  Issue: 11 )

Date of Publication:

Jun 2012

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.