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PDN analysis of TSV based decoupling capacitor stacked chip (DCSC) in 3D-ICs

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3 Author(s)
Eunseok Song ; Dept. of Electr. Eng., KAIST, Daejeon, South Korea ; Jun So Pak ; Joungho Kim

In this paper, we introduce a new decoupling capacitor stacked chip (DCSC) with discrete capacitors and through-silicon-vias (TSVs) that can be implemented into a multi-stacked 3D-IC system. The core idea of the proposed TSV-based DCSC is stacking the decoupling capacitors such as a silicon-based NMOS capacitor and a discrete capacitor on the backside of a chip and connecting the capacitors to the chip-power distribution network (PDN) through TSVs. A new TSV based DCSC structure that has the advantages of chip-level NMOS capacitor (under several tens pH) and package-level decoupling capacitor (up to several uF) solutions, which represent the conventional decoupling capacitor solution, is proposed. The proposed DCSC is a proper structure for implementing into multi-stacked 3D-IC systems through using the TSV technology. In addition, 3D PDN impedance variations are analyzed according to the number of TSVs in a multi-stacked 3D-IC system that is applied to DCSC and its arrangement. It is possible to achieve a robust 3D PDN for the power noise by using a TSV based DCSC and by arranging power as many TSVs as possible uniformly.

Published in:

Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2011 IEEE

Date of Conference:

12-14 Dec. 2011