By Topic

3D integration technology and reliability challenges

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Kangwook Lee ; New Industry Creation Hatchery Center (NICHe), Tohoku University, Sendai, 980-8579 Japan ; Takafumi Fukushima ; Tetsu Tanaka ; Mitsumasa Koyanagi

Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of the super-chip are described. In addition, the reliability challenges such as the mechanical stress/strain and Cu contamination are discussed. Cu TSVs with the diameter of 20-μm induced the maximum compressive stress of ~1 GPa at the Si substrate adjacent to them after annealed at 300°C. Mechanical strain/stress and crystal defects were produced in extremely thin wafer of 10μm thickness not only during the thinning but also after the bonding using fine-pitch, high-density metal bump. The influences of Cu contamination from the back surface of the thinned wafer and Cu TSVs on device reliability were evaluated by C-t analysis. The C-t curves of MOS capacitors formed in the thinned wafer without IG layer were seriously degraded after annealed at 200°C. The DP stress-relief EG layer at the backside of the thinned wafer exhibited good Cu retardation performance. The C-t curves of the MOS trench capacitor with 10-nm thick Ta barrier layer in Cu TSV were severely degraded after the initial annealing at 300°C for 5min. The degraded C-t curve indicates that the generation lifetime of minority carrier is significantly reduced by Cu contamination.

Published in:

Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2011 IEEE

Date of Conference:

12-14 Dec. 2011