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A 29.5 to 31.7 GHz PLL in 65 nm CMOS technology

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5 Author(s)
Yangping Chen ; Univ. of Electron. Sci. & Technol. of China, Chengdu, China ; Kai Kang ; Tong Tian ; Wei Wang
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A 29.5 to 31.7 GHz fully integrated phase locked loop (PLL) is presented in this paper. An integrated voltage-controlled oscillator (VCO) and a set of high-speed dividers are used to accomplish all the frequencies. The shunt peaking inductors is added in the first CML divider to higher the operating frequency and lower the power consumption. The current steering charge pump is utilized to improve switching time and thus allow high-speed operation. The PLL can be locked from 29.5 to 31.7 GHz. The PLL including buffers consumes 48mW from 1.2/0.7 V supplies. The output spectrum shows spur suppression higher than 23 dBc. Fabricated in a 65 nm CMOS process, the PLL occupies a chip area of 1.44 mm2.

Published in:

Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2011 IEEE

Date of Conference:

12-14 Dec. 2011