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Scaling and device design for 3D-stackable NAND (3D NAND) flash memory are investigated. Control gate length (Lg) and spacing (Lspace) are paid attention since they can be separately varied in 3D NAND and significantly affect the cell area of the 3D NAND as well as the electrical characteristics. The requirements for the Lg and Lspace are derived from the 3D device simulation and the cell size to compete with the planar NAND. The simulations reveal that Lg=Lspace=20nm (40nm layer pitch) is achievable for BiCS type 3D NAND with the 90nm diameter hole. Programming voltage can be also reduced from 20V to 17V. Lg and Lspace should be the same to cope with the tradeoff between memory window and disturbance. If the number of stacked layers is 18 with the layer pitch of 40nm, the effective cell size of the 3D NAND corresponds to that of 15nm planar NAND technology.