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Static Noise Margin and Power-Gating Efficiency of a New Nonvolatile SRAM Cell Based on Pseudo-Spin-Transistor Architecture

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3 Author(s)
Shuto, Y. ; Imaging Sci. & Eng. Lab., Tokyo Inst. of Technol., Yokohama, Japan ; Yamamoto, S. ; Sugahara, S.

Static noise margin (SNM) and power-gating efficiency were computationally analyzed for our proposed nonvolatile SRAM (NV-SRAM) cell based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque MTJs (STT-MTJs). The NV-SRAM cell has the same SNM as an optimized 6T-SRAM cell. SNM was also evaluated for other recently-proposed NV-SRAM cells using STT-MTJs, and we showed that their SNMs were deteriorated owing to the effect of the constituent STT-MTJs. Break-even time (BET) and power efficiency were analyzed for the NV-SRAM cell using PS-MOSFETs. The BET can be successfully minimized by controlling the bias of the cell. The average power dissipation can be effectively reduced by power-gating (PG) executions, and the further reduction is made possible by introducing a sleep mode (which is a data retention mode using a low power supply voltage).

Published in:

Memory Workshop (IMW), 2012 4th IEEE International

Date of Conference:

20-23 May 2012