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A computationally stable quasi-empirical compact model for the simulation of MOS breakdown in ESD-protection circuit design

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5 Author(s)
Shiang Liang Lim ; Center for Integrated Syst., Stanford Univ., CA, USA ; Xin Yi Zhang ; Zhipeng Yu ; Beebe, S.
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This paper presents a simple-to-implement, semi-empirical model for circuit-level simulation of the MOS breakdown region, with application in ESD-protection circuit design. A new formulation for the multiplicative factor M, used to model avalanche current generation, shows good convergence properties when used in circuit simulators. The effects of source/drain series resistance, substrate resistance, and the parameters of the new M expression are described. We describe how to calibrate the parameters for an NMOS device. Finally, we compare the simulated results with experimental data.

Published in:

Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97., 1997 International Conference on

Date of Conference:

8-10 Sept. 1997