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CusNoC: Fast Full-Chip Custom NoC Generation

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1 Author(s)
Li, K.S. ; Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

We propose a full-chip synthesis methodology to construct custom network-on-chips (CusNoCs) for NoC-based systems. The proposed scheme generates irregular network topologies for application-specific designs with known communication demands. In this method, processors and the communication architecture can be synthesized simultaneously in the floorplanning process, and thus it is called CusNoC. CusNoC synthesizes CusNoC in two steps. The target network topology is first generated based on communication analysis. Processing elements are partitioned into groups such that the utility of routers will be maximized if a router is assigned to each group. In this way, the number of routers passed by a packet, or hops, is minimized, and so is the power consumption in the network. The final network topology is formed by properly connecting these groups. A wirelength-aware floor planning is then carried out to optimize circuit size as well as wirelength. Experimental results show that CusNoC produces custom NoCs with better performance than previous methods while the computation time is significantly shorter. This method is also more scalable, which makes it ideal for complicated systems.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:21 ,  Issue: 4 )