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Ultralow Specific On-Resistance Superjunction Vertical DMOS With High- K Dielectric Pillar

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9 Author(s)
Xiaorong Luo ; State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China ; Y. H. Jiang ; K. Zhou ; P. Wang
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A superjunction (SJ) VDMOS with a high-k (HK) dielectric pillar below the trench gate is proposed and investigated by simulation. The HK dielectric causes a self-adapted assistant depletion of the n pillar. This not only increases the n-pillar doping concentration and thus reduces the specific on-resistance (Ron, sp) but also alleviates the charge-imbalance issue in SJ devices. The HK dielectric weakens the lateral field and enhances the vertical field strength in a high-voltage blocking state, leading to an improved breakdown voltage (BV). Ion implantation through trench sidewalls forms narrow and highly doped n pillars to further reduce the Ron, sp. The Ron, sp decreases by 42%, and BV increases by 15% compared with those of a conventional SJ VDMOS.

Published in:

IEEE Electron Device Letters  (Volume:33 ,  Issue: 7 )