By Topic

Ultralow Specific On-Resistance Superjunction Vertical DMOS With High- K Dielectric Pillar

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Xiaorong Luo ; State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China ; Jiang, Y.H. ; Zhou, K. ; Wang, P.
more authors

A superjunction (SJ) VDMOS with a high-k (HK) dielectric pillar below the trench gate is proposed and investigated by simulation. The HK dielectric causes a self-adapted assistant depletion of the n pillar. This not only increases the n-pillar doping concentration and thus reduces the specific on-resistance (Ron, sp) but also alleviates the charge-imbalance issue in SJ devices. The HK dielectric weakens the lateral field and enhances the vertical field strength in a high-voltage blocking state, leading to an improved breakdown voltage (BV). Ion implantation through trench sidewalls forms narrow and highly doped n pillars to further reduce the Ron, sp. The Ron, sp decreases by 42%, and BV increases by 15% compared with those of a conventional SJ VDMOS.

Published in:

Electron Device Letters, IEEE  (Volume:33 ,  Issue: 7 )