Ultralow Specific On-Resistance Superjunction Vertical DMOS With High-$K$ Dielectric Pillar

A superjunction (SJ) VDMOS with a high-
k
(HK) dielectric pillar below the trench gate is proposed and investigated by simulation. The HK dielectric causes a self-adapted assistant depletion of the n pillar. This not only increases the n-pillar doping concentration and thus reduces the specific on-resistance (
R
_{on, sp}
) but also alleviates the charge-imbalance issue in SJ devices. The HK dielectric weakens the lateral field and enhances the vertical field strength in a high-voltage blocking state, leading to an improved breakdown voltage (BV). Ion implantation through trench sidewalls forms narrow and highly doped n pillars to further reduce the
R
_{on, sp}
. The
R
_{on, sp}
decreases by 42%, and BV increases by 15% compared with those of a conventional SJ VDMOS.