By Topic

3D IC test scheduling using simulated annealing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Chih-Yao Hsu ; Dept. Electrical Engineering National Taiwan University, Taiwan ; Chun-Yi Kuo ; James C. -M. Li ; Krishnendu Chakrabarty

Three-dimensional integrated circuits (3D ICs) have many advantages over traditional integrated circuits. Although 3D ICs have such advantages, there are many difficulties to be overcome. Testing for 3D ICs is regarded as the most difficult challenge. High power density in 3D ICs causes rising temperature, which may cause test yield loss. In this paper, we propose a thermal-aware test scheduling technique for 3D ICs. Our experimental results show that the maximum temperature in the test schedule of our proposed technique is under the temperature limit while the test length overhead is only 19%.

Published in:

VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on

Date of Conference:

23-25 April 2012