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Performance validation of dynamic-remapping-based task scheduling on 3D multi-core processors

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2 Author(s)
Chien-Hui Liao ; Dept. of Electr. Eng., Nat. Chaio Tung Univ., Hsinchu, Taiwan ; Hung-Pin Wen

Many heuristics applying Dynamic Voltage and Frequency Scaling (DVFS) techniques have been proposed for energy minimization on three-dimensional multi-core processors. However, most previous works were built upon a fixed task-to-core mapping where many slack spaces can be further improved. In our previous research, we proposed a dynamic remapping strategy, Iterative Dynamic Remapping (IDR), to enhance an energy-aware task-scheduling algorithm while considering transmission cost. In this paper, performance for IDR with consideration to transmission costs between cores is validated through comparison with a Quadratic-Programming-based (QP-based) method and a Genetic-Algorithm-based (GA-based) method. Experimental results show that, the IDR strategy can run at least five-order faster while achieving comparable performance on total energy consumption of the QP-based method. Compared to the GA-based method, the IDR strategy can run at least three-order faster while achieving comparable (or even better) performance on total energy consumption.

Published in:

VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on

Date of Conference:

23-25 April 2012