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Challenges and solutions in modern analog placement

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4 Author(s)
Tung-Chieh Chen ; Phys. Design Group, SpingSoft Inc., Hsinchu, Taiwan ; Ta-Yu Kuan ; Chung-Che Hsieh ; Chi-Chen Peng

The analog placement problem is to place devices without overlap and design-rule-correction (DRC) error under position constraints (e.g. symmetry, cluster) such that some cost metric (e.g. area, wirelength) is optimized. However, modern analog design challenges have reshaped the placement problem. A modern analog placer also needs to consider device layout-dependent-effect (LDE) and interconnect parasitic effect. Because of multiple objectives, it is impossible to decide the single best placement. In this paper, we first introduce our placer that can explore multiple placements under position constraints so that a designer can analyze the trade-off among different objectives. Then, we provide some future research directions for the modern analog placement problem.

Published in:

VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on

Date of Conference:

23-25 April 2012