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In this paper, a power-aware and low power multimedia processor is presented. A novel clock gating scheme and dynamic frequency selection (DFS) are implemented to minimize the power dissipation and it integrates 7-standards (H.264 / VC1 / RV / AVS / MPEG-1 / MPEG-2 / MPEG-4) with several resource-sharing techniques in both algorithmic and architectural levels so as to achieve significant area and power reduction. In this work, our proposal also adopts several fine-grain power scalability (FGPS) technologies which can reduce a noticeable power consumption. The processor supports a wide range of decoding resolution ranging from CIF to full-HD under the 20~288MHz of working frequency and 60fps of frame rate with 363 μW/fps of power dissipation at 1.2V supply voltage and fabricated using 40nm 1P7M CMOS process with core area 1.40 mm2.
Date of Conference: 23-25 April 2012