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A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism

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2 Author(s)
Ching-Hwa Cheng ; Dept. of Electronic Engineering, Feng Chia University, 100, Wenhwa Road, Seatwen, TaiChung, Taiwan, R.O.C. ; Jiun-In Guo

A high-speed dual-phase domino circuit design with high performance and reliable characteristics is proposed. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64-bit high-speed multiplier with a built-in performance adjustment mechanism has been successfully validated using TSMC 0.18um CMOS technology. The test chip shows a 2.7X performance improvement compared to the conventional static CMOS logic design. In addition, a cell-based synthesizable design CAD flow, with consideration of the skew-tolerant issue has been established. A latched type domino cell library with noise-alleviation, charge sharing, and crosstalk alleviation abilities was also developed to support the proposed design flow. Finally, a built-in performance adjustment mechanism is conducted within the design. This mechanism supports performance adjustment after chip fabrication, under clock skew considerations.

Published in:

VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on

Date of Conference:

23-25 April 2012