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A method of redundant clocking detection and power reduction at RT level design

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4 Author(s)
M. Ohnishi ; Sharp Corp., Tenri, Japan ; A. Yamada ; H. Noda ; T. Kambe

This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clockings which activate registers unnecessarily, we detect these clockings. They are detected from the difference of the numbers of incoming and outgoing data of a register. Then we introduce a gated-clock scheme to reduce the power consumption of the circuits using our estimation results. Experimental results demonstrate the accuracy of our method and the effect on power reduction.

Published in:

Low Power Electronics and Design, 1997. Proceedings., 1997 International Symposium on

Date of Conference:

18-20 Aug. 1997