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An area-efficient cross feedforward cascode compensation (CFCC) technique is presented for a three-stage amplifier. The proposed amplifier is capable of driving heavy capacitive load at low power consumption but not dedicated to heavy load currents or heavy resistive loading. The CFCC technique enables the nondominant complex poles of the amplifier to be located at high frequencies, resulting in bandwidth extension. The amplifier can be stabilized with a cascode compensation capacitor of only 1.15 pF when driving a 500-pF capacitive load, greatly reducing the overall area of the amplifier. In addition, the presence of two left-hand-plane (LHP) zeros in the proposed scheme improves the phase margin and relaxes the stability criteria. The proposed technique has been implemented and fabricated in a UMC 65-nm CMOS process and it achieves a 2-MHz gain-bandwidth product (GBW) when driving a 500-pF capacitive load by consuming only 20.4 μW at a 1.2-V supply. The proposed compensation technique compares favorably in terms of figures-of-merit (FOM) to previously reported works. Most significantly, the CFCC amplifier achieves the highest load capacitance to total compensation capacitance ratio (CL/CT) of all its counterparts.