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Test Structures for Characterization of Through-Silicon Vias

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5 Author(s)
Stucchi, M. ; Interuniv. Micro Electron. Center, Leuven, Belgium ; Perry, D. ; Katti, G. ; Dehaene, W.
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3-D chip stacking using through-silicon vias (TSVs) requires accurate characterization of the TSV, the thinned silicon, and the stacked dies. This paper proposes a set of test structures specifically designed to address the electrical characterization of TSV in terms of resistance, capacitance, leakage, yield, and their impact on the 2-D interconnects of the stacked dies. Examples of the use of these structures are presented, and the observed electrical behaviors are explained with the support of FIB cross-section images.

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Semiconductor Manufacturing, IEEE Transactions on  (Volume:25 ,  Issue: 3 )