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Exploiting instruction- and data-level parallelism

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2 Author(s)
Espasa, R. ; Univ. Politecnica de Catalunya, Barcelona, Spain ; Valero, M.

Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications

Published in:

Micro, IEEE  (Volume:17 ,  Issue: 5 )