Referenced Items are not available for this document.
Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications
Published in:
Micro, IEEE
(Volume:17
,
Issue:
5
)
Date of Publication: Sep/Oct 1997
- Page(s):
- 20 - 27
- ISSN :
- 0272-1732
- INSPEC Accession Number:
- 5717883
- Digital Object Identifier :
- 10.1109/40.621210
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Sep/Oct 1997
- Sponsored by :
- IEEE Computer Society
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