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FPGA implementation of the parity check node for min-sum LDPC decoders

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5 Author(s)
Gutierrez, F. ; Digital Commun. Res. Lab., Nat. Univ. of Cordoba, Cordoba, Argentina ; Corral-Briones, G. ; Morero, D. ; Goette, T.
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A typical high-speed decoder implementation for an LDPC may require hundreds or even thousands of variable and check node processors. Since check node processing unit (CNPU) is far more complex than variable processing unit, hardware requirements of CNPU has a big impact on the final decoder complexity. Here, an FPGA implementation of the soft parity check node for min-sum LDPC decoders is analyzed. The hardware cost and speed of the main block of CNPU, which finds the two smallest input values, is thoroughly studied for different numbers of input values with different bit-widths. Experiments for an FPGA implementation demonstrate that hardware cost and speed vary with the number of input values in the same way as they do for an ASIC implementation. Furthermore, it is shown that more than 60% of the hardware resources of the CNPU is used for finding the two smallest input values.

Published in:

Programmable Logic (SPL), 2012 VIII Southern Conference on

Date of Conference:

20-23 March 2012