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FPGA implementation of large-scale matrix inversion using single, double and custom floating-point precision

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4 Author(s)
Arias-Garcia, J. ; Depts. of Mech. Eng., Univ. of Brasilia Brasilia, Brasilia, Brazil ; Llanos, C.H. ; Ayala-Rincon, M. ; Jacobi, R.P.

This work presents an architecture to compute matrix inversions in a hardware reconfigurable FPGA using different floating-point representation precision: single, double and 40-bits. The architectural approach is divided into five principal parts, four modules and one unit, namely Change Row Module, Pivo Module, Matrix Elimination Module, Normalization Module and finally the Gauss-Jordan Control-Circuit Unit. This division allows the work with other smaller arithmetic units that are organized in order to maintain the accuracy of the results without the need to internally normalize and de-normalize the floatingpoint data. The implementation of the operations and the whole units take advantage of the resources available in the Virtex-5 FPGA. The error propagation and resource consumption of the implementation, specially the internal RAM memory blocks that are used, constitute improvements when compared with previous work of the authors and other more elaborated architectures whose implementations are significantly more complex than the current one and thus unsuitable for its application. The approach is validated by implementing benchmarks based on solutions in FPGA and software (e.g. Matlab) implemented previously.

Published in:

Programmable Logic (SPL), 2012 VIII Southern Conference on

Date of Conference:

20-23 March 2012

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