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A 12-b 30-MS/s pipelined ADC is realized using single-stage, low-gain, class-AB amplifiers, which can dynamically provide the load currents without large static currents. In addition, the amplifiers are power cycled and turned on only during residue amplification to enable further power savings. Nonlinear errors due to finite gain are addressed using a deterministic digital background calibration scheme. The amplifier's transfer function is piecewise modeled in our calibration scheme using three third-order polynomial functions (splines) for low computational overhead. The presented ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near Nyquist. The corresponding figure of merit is 72 fJ/conversion-step.
Date of Publication: Sept. 2012