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Capacitive-coupling-based simultaneously bi-directional transceivers for chip-to-chip communication in three-dimensional integrated circuits are presented. By employing a 4-level signaling strategy with a novel cascaded capacitor configuration, the proposed transceivers can transmit and receive data simultaneously through a single inter-chip coupling capacitor, and effectively improve the throughput per interconnect. In this work, the proposed cascaded capacitor structure and its signaling strategy are discussed in details and circuit solutions for transceivers are presented. A parasitic shielding technique is employed in the electrode design to improve signal swings without area overheads. A 16μm×20μm electrode provides the voltage margin as large as 195 mV at 1.2 V supply (verified by post-layout simulation) for signal sensing and recovery. The proposed transceivers are designed in a commercial 65-nm complementary metal-oxide-semiconductor technology.