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Key enabling technologies of 300mm 3DIC process integration

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17 Author(s)
Pei-Jer Tzeng ; Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan ; Yu-Chen Hsin ; Jui-Chin Chen ; Shang-Chun Chen
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Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules are also provided as process guidelines.

Published in:

VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on

Date of Conference:

23-25 April 2012