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The design flexibility offered by current Field Programmable Gate Array (FPGA) technology allows system designers to partition application functionalities between hardware and software to meet the design goals such as area, power consumption, etc. Efficient partitioning is a nonpolynomial problem, usually performed by Design Space Exploration (DSE), where certain metrics of the design space must be set by the designer in order to ensure exploration feasibility. This paper describes a customizable processor architecture to be integrated on a DSE tool for Multi-Processor Systems-on-Chip (MPSoCs). The proposed architecture is a multi-threading processor whose micro-architecture can be finetuned and whose ISA can be extended, allowing its use as a processor template for hardware/software co-design. Using benchmarks from the MiBench suite, results on how the performance/area/power tradeoffs are explored by the configuration possibilities are shown, describing the processor's several micro-architectural features and how they were designed with configurability as a goal.
Date of Conference: 19-21 March 2012