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Design of a FPGA-based Timing Sharing Architecture for Sound Rendering Applications

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7 Author(s)
Tan Yiyu ; Center for Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan ; Inoguchi, Y. ; Sato, Y. ; Iwaya, Y.
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Sound rendering applications are data-intensive and memory-intensive as a sound space increases. To speed up computation and extend the simulated area, a sound rendering system based on the two-dimensional Digital Huygens Model (DHM) with timing sharing architecture is designed and implemented by a Field Programmable Gate Array (FPGA) chip XC5VLX330T. Compared with the DHM system with the traditional parallel architecture, the proposed system implemented by a FPGA chip extends about 20 times in simulated area, and speeds up 1.47 times against the software simulation carried out in a computer with an AMD Phenom 9500 Quad-core processor (2.2 GHz) and 4GB RAM. The system is relatively easy to cascade many FPGA chips to work in parallel in real applications.

Published in:

Information Technology: New Generations (ITNG), 2012 Ninth International Conference on

Date of Conference:

16-18 April 2012