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A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing

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4 Author(s)
Schlottmann, C.R. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Shapero, S. ; Nease, S. ; Hasler, P.

We present a field-programmable analog array designed for accurate low-power mixed-signal computation. This 25-mm2 350 nm-CMOS reconfigurable analog IC incorporates digital enhancements to increase compatibility in embedded mixed-signal systems. The chip contains 78 computational analog blocks (CABs) which house a variety of processing elements. There are 36 general CABs with hundreds of common analog primitives for computation, 18 digital-to-analog converter (DAC) CABs, each with 8-b compilable DAC capabilities, and 24 vector-matrix multiplier CABs, for low-power parallel processing. A floating-gate routing matrix connects these analog elements to one another, both within individual CABs and between CABs. To facilitate digital interfacing and dynamic reconfigurability, we included a novel network of volatile switches based on digital shift and select registers that control analog switches. These dynamically controlled switches span all of the rows and columns of the internal routing, allowing for run-time system modification and scanning I/O. The digital registers can also double as on-chip memory. We introduce a new hybrid floating-gate switch matrix, which includes switches that eliminate previously observed mismatch issues to provide highly precise computation. To highlight the potential of this digitally enhanced analog processor, we demonstrate a dynamically reconfigurable image transformer, an arbitrary waveform generator, and a mixed-signal FIR filter.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 9 )