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In this paper we discuss a theoretical approach to do early assessment of the area and power consumption of hardware accelerators for elliptic curve cryptography. For evaluation we developed several different one clock multipliers as building block for the final serial multipliers. The former are evaluated concerning their efficiency in comparison to literature and the results of our assessment technique are compared with synthesis results. Since the application areas we are interested in are embedded systems, pervasive computing or wireless sensor networks we investigated serial multipliers in order to achieve reduced area and energy consumption compared to the single clock multipliers. Our evaluation clearly shows that our approach provides good hints to select well suited implementation candidates.
Date of Conference: 7-10 May 2012