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Challenges for patterning process models applied to large scale

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1 Author(s)
Sturtevant, John L. ; Mentor Graphics Corporation, 8005 SW Boeckmann Rd., Wilsonville, Oregon 97070

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1116/1.3695646 

Full-chip patterning simulation has been utilized in semiconductor manufacturing for more than ten years, and has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasirigorous optical models and semiempirical resist and etch process models. There has been steady improvement in the predictive power and computational efficiency of the patterning models used in full chip simulation tools, and this paper will review this progress as well as the factors that ultimately limit the predictive capability of such models. In addition, this paper will outline the new process simulation challenges that are emerging as the industry approaches sub-0.25 k1 patterning. These challenges lie principally in improving accuracy and predictive capability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:30 ,  Issue: 3 )