Referenced Items are not available for this document.
Nonbinary low-density parity-check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity iterative decoding algorithms have been proposed, the VLSI implementation of NB-LDPC decoders still remains a big challenge due to its high complexity and long latency. In this brief, a highly efficient check node processing scheme, which the processing delay greatly reduced, is proposed for Min-max decoding algorithm. Thereafter, an efficient check node unit (CNU) can be designed. Compared with previous works, the latency of the CNU could be reduced to less than 52%. In addition, a decoder for a (620, 310) NB-LDPC code is designed to demonstrate the efficiency of the presented techniques.
Published in:
Circuits and Systems II: Express Briefs, IEEE Transactions on
(Volume:59
,
Issue:
6
)
Date of Publication: June 2012
- Page(s):
- 381 - 385
- ISSN :
- 1549-7747
- INSPEC Accession Number:
- 12786471
- Digital Object Identifier :
- 10.1109/TCSII.2012.2195058
- Product Type:
- Journals & Magazines
- Date of Publication :
- 23 May 2012
- Date of Current Version :
- 12 June 2012
- Issue Date :
- June 2012
- Sponsored by :
- IEEE Circuits and Systems Society
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