Skip to Main Content
We introduce a dynamically reconfigurable DCT architecture system that allows us to select optimal implementations based on bitrate and dynamic power constraints. For our approach, we first compute Pareto-optimal hardware realizations that are assessed in terms of reconstructed image quality, bitrate and dynamic power. The space of Paretooptimal realizations are generated by varying both the number of non-zero DCT coefficients and the quality factor for the quantization table. From the generated hardware realizations, we then select the Pareto-optimal cases and discard all other cases. For each bitrate and dynamic power constraint, we use a dynamic partial reconfiguration (DPR) controller to implement the optimal DCT architecture. We test our approach using leave-one-out on the LIVE database, and implement our system on a Virtex-5 FPGA and demonstrate its performance using different bitrate and dynamic power constraints.
Date of Conference: 22-24 April 2012