By Topic

Using Transmission Lines for Global On-Chip Communication

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Carpenter, A. ; Electr. & Comput. Eng. Dept., Binghamton Univ., Vestal, NY, USA ; Jianyun Hu ; Jie Xu ; Huang, M.
more authors

The growing number of cores in chip multiprocessors increases the importance of interconnection for overall system performance and energy efficiency. Compared to traditional distributed shared-memory architectures, chip-multiprocessors (CMPs) offer a different set of design constraints and opportunities. As a result, a conventional packet-relay multiprocessor interconnect architecture is a valid, but not necessarily optimal, design point. Worsening wire delays, energy-inefficient routers, and the decreased importance of in-field scalability, make the conventional packet-switched network-on-chip a less attractive option. An alternative solution uses well-engineered transmission lines as communication links. These transmission lines, along with simple, practical circuits using modern complementary metal-oxide-semiconductor technology, can provide low latency, low energy, high throughput channels which can be used as a shared-medium point-to-point link. The design of the transmission lines and transceiver circuits has important architectural impact. This paper includes a first-step design effort for these components, particularly when used for a globally shared-medium bus. For medium-scale CMPs, this interconnect backbone can eliminate the need for packet switching and provide energy, as well as performance benefits when compared to a conventional mesh interconnect. We will provide a design of such a system from the ground up, including design of the transmission lines, transceiver circuits, and a simple, yet effective, architectural design for a shared-medium interconnect, and show that such a design can be a compelling alternative to packet-switched networks for CMPs.

Published in:

Emerging and Selected Topics in Circuits and Systems, IEEE Journal on  (Volume:2 ,  Issue: 2 )