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A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process

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7 Author(s)
Chiu-Wang Lien ; Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Haw-Yun Wu ; Cheng-Wei Tsai ; Chen-Mei Huang
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A new fully logic process compatible 2T multitime programmable (MTP) memory cell has been introduced for embedded logic nonvolatile memory (NVM) applications. The cell adopts a novel contact coupling gate structure as an additional control gate for highly efficient operation and high-density memory applications. A new 2T n-channel MTP 2-Kb memory test chip has been also successfully demonstrated on pure 0.18- CMOS logic process without extra masking or process step. Furthermore, the embedded 2T MTP cell performs an efficiently program/erase operation by CHE injection and FN tunnel with highly reliable endurance and retention characteristics.

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Electron Devices, IEEE Transactions on  (Volume:59 ,  Issue: 7 )