Non-Uniformly Tiled CMOS Image Sensors for Efficient On-Chip Image Compression

We present a complementary metal-oxide semiconductor (CMOS) image sensor with non-uniform pixel placement that enables a highly efficient calculation of the discrete cosine transform (DCT), which is the most mathematically intensive step of an image compression algorithm. This technique is based on the arithmetic Fourier transform (AFT), which has been shown to be five times more computationally efficient than DCT derivation methods commonly used. In this paper, the focus is on the basic theory and algorithm as well as the sensitivity of the method to image sensor fixed pattern noise (FPN). The architecture and circuits have been implemented in a conventional CMOS process. The method has been demonstrated in the current prototype and results that enable an assessment of the sensitivity to FPN have been obtained.