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Low Power and Enhanced Noise Margins SRAM Using Novel Asymmetric FinFETs

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3 Author(s)
Kaushik, N. ; Dept. of Phys., Indian Inst. of Technol. - Roorkee, Roorkee, India ; Kaur, D. ; Kaushik, B.K.

This paper proposes a asymmetric FinFET (Fin shaped Field Effect Transistor) for robust and low power SRAM (Static Random Access Memory). This FinFET device uses Asymmetric Drain (AD), Asymmetric Drain Spacer Extension (ADSE) and Asymmetric Lateral Diffusion (ALD) techniques. The proposed structure exploits asymmetrical behavior of current to improve read-write stability for SRAM without compromising the cell area. As the asymmetry in Ids (drain to source) and Isd (source to drain) increases, improvement is observed in read, write and static noise margins. The write noise margin (WNM) and read noise margin (RNM) behavior is contradictory to each other, increase in one leads to decrease in other. It has been observed that by using asymmetric FinFETs altogether an overall improvement in static, read and write noise margins are 23.5, 19.3 and 12.4, percent respectively. Reduction in Average power is observed 21 percent.

Published in:

Communication Systems and Network Technologies (CSNT), 2012 International Conference on

Date of Conference:

11-13 May 2012