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A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures

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2 Author(s)
Nandakumar, V.S. ; Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA, USA ; Marek-Sadowska, M.

In this paper, we study the network-on-chip (NoC) implemented with new vertical slit field effect transistors (VeSFETs). The unique properties of VeSFET circuits allow for very efficient power saving techniques that are not possible in complementary metal-oxide-semiconductor-based homogeneous 3-D NoCs. We demonstrate that the proposed 3-D hybrid architecture shows significant improvements in all network parameters including latency, power, and energy consumption compared to other practical 3-D NoCs.

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Emerging and Selected Topics in Circuits and Systems, IEEE Journal on  (Volume:2 ,  Issue: 2 )