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A 1 TB/s 1 pJ/b 6.4 {\rm mm}^{2}/{\rm TB/s} QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM

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3 Author(s)
Miura, N. ; Dept. of Electr. Eng., Keio Univ., Yokohama, Japan ; Saito, M. ; Kuroda, T.

1 TB/s 1 pJ/b 6.4 mm2 /TB/s QDR inductive-coupling interface between 65-nm complementary metal-oxide-semicon ductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <;10-10 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.

Published in:

Emerging and Selected Topics in Circuits and Systems, IEEE Journal on  (Volume:2 ,  Issue: 2 )

Date of Publication:

June 2012

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